The present invention relates in general to integrated circuit dice and more particularly to a method of metallization for wafer level electrical testing of integrated circuit dice.
One factor that has been identified as critical to the continued success of the semiconductor industry, is the ability to identify a "known good die" (KGD). Typically, a KGD is one which has not only passed some preliminary electrical test, but also one in which there is essentially 100% confidence that it will function when packaged and made part of a customer's application. This must be true whether the die is packaged singly or as part of a multichip module (MCM).
The importance of having a KGD for inclusion in a MCM can be illustrated by comparing the test yield of a MCM assembled with KGD to that of a MCM assembled with dice having individual die yields of 95%. The test yield of a MCM containing ten die is a function of the individual die yield and the assembly yield of the MCM. Thus, where the individual die yields are 95%, the test yield of the MCM is at best the product of the individual die yields or 59.8%. This result is unacceptable. On the other hand, if each of the ten die were a KGD, the individual die yield would be essentially 100%. Thus the MCM yield would only be a function of module assembly operations, and could approach 100%.
One common method of determining KGD, is to first test each die individually, or in small aggregates, using costly wafer probe equipment while the dice are in wafer form. The dice are then singulated, or separated into individual die, and each die is packaged for a reliability testing procedure commonly referred to as burn-in. It has been found that the early failure or "infant mortality" can be predicted to occur within a particular period of time. Therefore burn-in testing involves testing the integrated circuit for that particular period of time, typically at elevated temperatures. The cost of this type of testing is high due to the cost of singulation, packaging and individual die burn-in.
Methods for reducing the cost of testing and burn-in have been under intense investigation. One such method is a subject of U.S. Pat. No. 5,399,505, entitled "METHOD AND APPARATUS FOR PERFORMING WAFER LEVEL TESTING OF INTEGRATED CIRCUIT DICE", issued Mar. 21, 1995 to Edward C. Dasse et al., and assigned to the same assignee, Motorola, Inc. The '505 patent is hereby incorporated by reference. The patent describes, in part, a semiconductor wafer having integrated circuit dice, wafer conductors and wafer test pads formed thereon. More specifically, the patent discloses, among other things, a first method that is suitable for dice that will be wire bonded when packaged, and a second method suitable for dice that will have bumps formed overlying bonding pad areas on each die.
While the methods of U.S. Pat. No. 5,399,505 meet the needs of the industry as described therein, they are somewhat inflexible in that they require that each wafer and the integrated circuit dice thereon be committed to a specific type of assembly process at a step just prior to the formation of a first metal or first conductive layer. This is well before testing and burn-in.
Therefore, it would be advantageous to have a method for wafer level testing that would allow for flexibility in the ultimate packaging of the dice and not require any advance commitment. In addition, it would be advantageous to develop a method that minimizes the number of process steps required, thus making the process more cost effective.